Method and device for processing an erase counter

ABSTRACT

A embodiment relates to a method for processing an erase counter comprising erase counter fields, the method comprising the steps of (i) determining an unused erase counter field; (ii) writing a selection code and an address information in the unused erase counter field, wherein the selection code and the address information are combined to determine at least one physical address of a memory.

BACKGROUND OF THE INVENTION

Embodiments of the present invention relate to processing of an erasecounter that enables monitoring of data manipulation.

SUMMARY

A first embodiment relates to a method for processing an erase countercomprising erase counter fields, the method comprising the steps:

-   -   determining an unused erase counter field;    -   writing a selection code and an address information in the        unused erase counter field;    -   wherein the selection code and the address information are        combined to determine at least one physical address of a memory.

A second embodiment relates to a device comprising:

-   -   an erase counter comprising several erase counter fields;    -   a processing unit that is arranged for processing the erase        counter by        -   determining an unused erase counter field;        -   writing a selection code and an address information in the            unused erase counter field;        -   wherein the selection code and the address information are            combined to determine at least one physical address of a            memory.

A third embodiment relates to a device for processing an erase countercomprising erase counter fields, the device comprising:

-   -   means for determining an unused erase counter field;    -   means for writing a selection code and an address information in        the unused erase counter field;    -   means for wherein the selection code and the address information        are combined to determine at least one physical address of a        memory.

A forth embodiment is directed to a computer program product directlyloadable into a memory of a digital processing device, comprisingsoftware code portions for performing the steps of the method describedherein.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments are shown and illustrated with reference to the drawings.The drawings serve to illustrate the basic principle, so that onlyaspects necessary for understanding the basic principle are illustrated.The drawings are not to scale. In the drawings the same referencecharacters denote like features.

FIG. 1 shows an exemplary diagram of an erase counter storage comprisingseveral erase counter fields;

FIG. 2 shows an exemplary structure of an erase counter field and howthe erase counter field may be represented in a physical memorystructure, e.g., a flash memory;

FIG. 3 shows an exemplary table comprising 32 physical sectors (numbered0 to 31), each having a physical sector address, wherein a logicaladdress is provided that allows combining several sectors, e.g., for acombined (e.g., parallel) erase operation;

FIG. 4 shows an exemplary flow diagram indicating a routine that may beconducted once per erase operation, even in case several portions (e.g.,sectors or page) of a memory are erased.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Non-volatile memories (NVMs) can be programmed and erased by varioussoftware applications. The memory may be organized in a way that a groupof bits are erased or programmed together. For example, a sector of thememory may be erased or a page of the memory may be programmed. Forexample, the page may comprise several bits and the sector may compriseseveral pages.

The examples presented herein allow determining how many erase cycleswere conducted on a single sector or a group of sectors. Thisinformation may be useful to determine whether the memory has beentampered with, in particular whether the memory was subject tounauthorized changes.

It is noted that the sector mentioned herein is an example of a portionof a memory that can be erased, wherein the sector comprises at leastone bit, in particular several bits or several pages. The memorymentioned may in particular be a memory device.

An erase counter concept may be used in any device that has persistentand re-programmable memory, e.g., NAND/NOR Flash, RRAM, MRAM, FeRAM. Itmay also be applicable for hard drives that have certain sectors setaside as erase counters to monitor if other sections have been erasedand/or re-written.

Use cases may relate to scenarios with re-programmable firmware.Exemplary scenarios are: mobile phones, washing machines, engine controlmodules (e.g., in the automotive field), manufacturing robots in anassembly line, DVD players, game consoles, FPGA devices, etc.

The examples described herein hence in particular provide a non-volatileerase counter to monitor data manipulation.

The memory area is in particular non-volatile. The memory area may bearranged such that it is read-only for application software (i.e.applications running on a device cannot modify this memory area as theywish).

Hence, the erase counter can be used to detect and prove manipulation ofa software. For example: A ninth version of an official software releasemay be associated with eight erase operations which should be indicatedby the erase counter. A higher number of erase cycles indicated by theerase counter may be a sign of unauthorized software manipulation.

Hence, the solution presented may be used for security applications orin order to supply evidence of tampering.

For example, the erase counter may be incremented when a sector is aboutto be erased. The modification of the erase counter may preferably beachieved without any chance of manipulation by the application software.Modification of the erase counter may preferably be encapsulated from anoutside programming interface so that it cannot be avoided that anyerase operation increments the erase counter.

Advantageously, the erase counter may be implemented in a way that itcannot be deleted by a customer; in particular the erase counter may bearranged such that it can only be deleted prior to the product, inparticular the memory device, being shipped to the customer.

Tampering with the content of the memory (device) can be detected bystoring the value of the erase counter (such value may be stored insidethe memory device and/or external to the memory device) and compare thisvalue with the actual value of the erase counter. The value of the erasecounter may be stored after shipping of the memory device and/or afteran authorized change (e.g., official update) of the software.

The erase counter may be non-erasable. For example, the erase countermay be stored in a memory area that cannot be erased or that can beconfigured such that a simple erase of this memory area is not feasible.There may be one erase counter per logical portion, e.g., per at leastone logical sector, of the memory. In order to update the erase counter,the erase counter may be read, incremented and written to its memoryarea. Such update may be conducted per sector.

A write operation may consume significantly more time than a readoperation. Erasing several sectors is thus time consuming due to thelengthy write operations involved. Erase procedures may have to beaborted via a special command that allows for an interruption in orderto conduct other operations. Such other operations may require the eraseoperation to have a short abort time, which is difficult to meet due toits lengthy write operations.

According to an example, a selection code may be used to select at leastone portion of memory, e.g., a sector or a page. The at least oneportion selected by the selection code may be erased. The at least oneportion of memory may in particular comprise several portions of memory.The erase may be conducted in parallel for at least some of the severalportions of memory.

An erase counter may be provided that is updated via a search loop witha subsequent write operation.

The erase counter may be stored in an erase counter storage, whichcomprises several erase counter fields. Each of the erase counter fieldscomprises

-   -   an address information and    -   the selection code.

The selection code may be written to the erase counter field.

FIG. 1 shows an exemplary diagram of an erase counter storage 101comprising several erase counter fields 102 to 105. The erase counterstorage 101 may be part of a random access memory (e.g., flash RAM orNVM). The erase counter storage 101 is used by allocating the firstcounter field 102; with a subsequent erase cycle, the next counter field103, etc. is used. As an advantage, a single counter field 102 to 105can be associated with an erase operation that is applied to severalmemory portions, e.g., sectors.

FIG. 2 shows an exemplary structure of one of the erase counter fields102 to 105 and how the erase counter fields 102 to 105 may be stored inthe memory, e.g., a flash memory.

An erase counter field 203 comprises a selection code 201 and an addressinformation 202. According to the example shown in FIG. 2, the erasecounter field 203 has the following value:

-   -   the selection code 201 comprising a range of bits 4 to 0 has the        value “00011”; and    -   the address information 202 comprising a range of bits 7 to 0        has the value “00010100”.

A line 204 of bits shows an example as how to store the erase counterfield in a physical flash memory. In this example, each single bit isencoded by three physical bits to add redundancy (i.e. a bit “0” of theerase counter field 203 is coded as “000” and a bit “1” of the erasecounter field 203 is coded as “111”): In case one of the bits does notshow the correct value (e.g., due to a physical defect), a majoritydecision based on all three bits can be made to still arrive at thecorrect bit “0” or “1”. This may be useful in case no further errorcorrection code is available and/or this further error correction codeis optional and deactivated. It is noted that a number of bits differentfrom three may be used for coding a single bit of the erase counterfield 203.

FIG. 3 shows an exemplary table comprising 32 physical sectors (numbered0 to 31), each having a physical sector address 301. In addition, alogical sector 302 is provided that allows combining several sectors,e.g., for a combined (e.g., parallel) erase operation.

Such combining may be achieved via the selection code and the addressinformation (as also indicated above). In the current example, thesector address is composed of eight bits provided by the addressinformation and the multiple sector addresses are identified via fivebits of the selection code.

The selection code may be aligned at the least significant bit (LSB)with the address information and it may be used to determine the sectorsto be erased. For example, if the bit of the selection code thatcorresponds to the position of the address information is “0”, the bitof the address information remains unchanged; if the bit of theselection code that corresponds to the position of the addressinformation is “1” then the bit of the address information may be either“0” or “1”. Hence, the selection code can be used for selecting either asingle physical address or a multitude of physical addresses based onthe address information.

Example 1 Erase of Logical Sector 5

The address information and the selection code are determined asfollows:

Address information: 00000101

Selection code: 00000

A bitwise OR operation results in the following sector address that iserased:

Sectors erased: 00000101

Example 2 Erase of Logical Sector 16

The address information and the selection code are determined asfollows:

Address information: 00011000

Selection code: 00011

A bitwise OR operation results in the following sector addresses thatare erased:

Sectors erased: 00011000

-   -   00011001    -   00011010    -   00011011

Hence, this address information and the selection code can be associatedwith an erase operation of the physical sectors 24 to 27.

Example 3 Erase of Logical Sectors 14 and 15

The address information and the selection code are determined asfollows:

Address information: 00010100

Selection code: 00011

A bitwise OR operation results in the following sector addresses thatare erased:

Sectors erased: 00010100

-   -   00010101    -   00010110    -   00010111

Hence, this address information and the selection code can be associatedwith an erase operation of the physical sectors 20 to 23.

Example 3 is also the exemplary allocation of the erase counter field203 in FIG. 2, wherein the sector address 301 corresponds to the addressinformation 202.

It is an advantage of the solution presented that only a single writeoperation to the erase counter storage is required even in case severalportions of memory (e.g., sectors or pages of a memory) are erased. Thissolution is highly flexible and allows for a multitude of combinationsin order to logically address a physical memory structure.

FIG. 4 shows an exemplary flow diagram indicating a routine that may beconducted once per erase operation, even in case several portions (e.g.,sectors or page) of a memory are erased.

In a step 401, a counter x is initialized (e.g., set to 0). In a step402 the x-th erase counter field (also referred to as “erase counterfield number x” or “erase counter field #x”) in the erase counterstorage is read. In a step 403 it is checked whether this erase counterfield number x has already been used, which may be determined in case itshows values other than “0”. If this is the case, it is continued with astep 404 incrementing the counter x. In a step 405 it is checked whetherthe end of the erase counter storage is reached. If this is the case,the procedure ends in a step 405. Optionally, an error or an informationmay be issued indicating an overflow of the erase counter storage. Ifthe end of the erase counter storage is not reached, it is branched tothe step 402 and the erase counter field number x is read.

If step 403 reveals that the erase counter field number x has notalready been used, it is continued with a step 407 which indicates thatan available erase counter field was found in the erase counter storage.In a subsequent step 408 the erase counter field found is written withthe selection code and the address information. Next, the procedure endsin the step 406.

Optionally, the actual erase operation based on the selection code andthe address information can be conducted subsequent or in advance tostep 408.

The steps 401 to 405 can be regarded as a search routine 409. The searchroutine 409 can be accelerated, e.g., via a binary search algorithm.

The solution shown in FIG. 4 bears the advantage that the update of theerase counter storage is divided into a fast search routine 409(including read operations directed to the erase counter fields) and asingle write operation 408 to the erase counter storage. This enables afast update routine for the erase counter storage.

Also, the examples presented allow for a high degree of flexibility,because single or multiple portions of the memory (e.g., sectors orpage) can be addressed via one selection code. Hence, this selectioncode can be used to erase several of these portions. Preferably, theselection code and the address information are stored in the erasecounter storage after the erase operation has been triggered, inparticular after the erase operation has been conducted.

The examples suggested herein may in particular be based on at least oneof the following solutions. In particular combinations of the followingfeatures could be utilized in order to reach a desired result. Thefeatures of the method could be combined with any feature(s) of thedevice, apparatus or system or vice versa.

A method is suggested for processing an erase counter comprising erasecounter fields, the method comprising the steps:

-   -   determining an unused erase counter field;    -   writing a selection code and an address information in the        unused erase counter field;    -   wherein the selection code and the address information are        combined to determine at least one physical address of a memory.

The unused erase counter field may be determined via a search operation.

Advantageously, a single selection code can be used to determine one orseveral physical addresses of the memory. Hence, an erase operation maybe directed to several portions, e.g., sectors, of a memory which can bereflected by a single update of the erase counter.

An exemplary implementation of the erase counter uses a thermometer code(or unary code). For example, each erase counter field may be used toindicate an single piece or increment of the erase counter and in thisregard correspond to a single bit of the thermometer code.

Unary coding, also referred to as thermometer code, is an entropyencoding that represents a natural number, k, with k ones followed by azero (if natural number is understood as non-negative integer) or withk−1 ones followed by a zero (if natural number is understood as strictlypositive integer). For example, the number 5 is represented as 111110 or11110. Some representations use k or k−1 zeroes followed by a one. Theones and zeroes are interchangeable without loss of generality. Unarycoding is both a Prefix-free code and a self-synchronizing code (see,e.g., http://en.wikipedia.org/wiki/Thermometer_code).

It is noted that the erase counter may be stored in an erase counterarea of a memory.

It is also noted that the counter fields may be arranged in an ascendingorder such that the counter fields may be set one after another torepresent an increasing count of the erase counter. The counter fieldsmay thus be used to successively fill the erase counter, wherein settinga single counter field may be an increment of such erase counter.Preferably, the erase counter can only be set, not re-set. This allowsdetermining the number of erase cycles or erase operations applied to aportion of a memory, e.g., a sector or a page of the memory.

It is further noted that incrementing the erase counter may comprise anincrease by one or an increase by a value larger than one.

Advantageously, the solution allows determining how many erase cycleswere conducted on said portion of the memory, i.e. on a single sector ora group of sectors of the memory. This information can be used todetermine whether the memory has been tampered with, in particularwhether the memory was subject to unauthorized changes.

It is further noted that erase cycles on a hard drive or a portion ofthe hard drive (e.g., sector) can be counted via the erase counter asdescribed herein.

In an embodiment, the physical address of the memory is directed to asector or to a page of the memory.

In an embodiment, at least one sector or at least one page of the memoryis subject to an erase operation.

In an embodiment, the erase operation is triggered or conducted prior tosaid processing of the erase counter or after said processing of theerase counter.

In an embodiment, the selection code and the address information arecombined to determine several physical addresses of the memory.

In an embodiment, the selection code determines one or several physicaladdresses within the address information.

The selection code may in particular provide a mask that can be combinedwith the address information to determine—within a scope provided by theaddress information—several physical addresses of the memory via asingle selection code.

In an embodiment, the method further comprises the steps:

-   -   aligning the selection code at the least significant bit with        the address information    -   determining at least one physical address that is subject to an        erase operation by combining the selecting code and the address        information, wherein        -   a first of the selection code indicates that a corresponding            bit of the address information remains unchanged or        -   a second value of the selection code indicates that a            corresponding bit of the address information may be either            “0” or “1”.

In an embodiment, the first value is “0” and the second value is “1”.

In an embodiment, determining an unused erase counter field comprisesconducting a search operation for the unused erased counter field in anerase counter storage provided for the erase counter.

In an embodiment, the erase counter is incremented by writing theselection code and the address information to the unused erase counterfield.

The erase counter may have a predetermined number of erase counterfield, which may initially be all empty. The erase counter can be set bywriting data to the first free erase counter field. The erase counter isincremented by writing data to the next free erase counter field. Theerase counter fields may be used subsequently to increase the count ofthe erase counter. As an alternative, the erase counter fields may beused according to a predetermined scheme to fill the erase counter.Advantageously, the erase counter cannot be reset by an applicationsoftware.

In an embodiment, the erase counter is associated with a portion of amemory, in particular a non-volatile memory, and wherein an eraseoperation applied to said portion of the memory triggers incrementingthe erase counter.

In an embodiment, the erase counter is part of a non-volatile memory,wherein the memory of the erase counter is not accessible or read-onlyto an application software.

In an embodiment, the erase counter is a non-volatile erase counter.

In an embodiment, each logical bit of the erase counter field comprisesseveral physical bits, wherein a majority decision is made based on theseveral physical bits for the corresponding logical bit.

The majority decision is an example of how to utilize the redundancy ofthe several physical bits that are used to represent a single logicalbit. However, other operations may be applied accordingly. It is alsopossible to use a code with redundancy or an error detection code and/oran error correction code to determine if the logical bits.

In particular, at least some (or all) bits of the selection code and/orthe address information may be mapped to at least two physical bits eachfor redundancy purposes.

In an embodiment, the method further comprises the steps:

-   -   reading the erase counter and storing it in a register;    -   searching for the unused erase counter field;    -   writing the selection code and the address information in the        unused erase counter field; and    -   writing the register back to the erase counter.

In an embodiment, the method comprises the step:

-   -   indicating a warning or an error in case writing the register        back to the erase counter was not successful.

In an embodiment, the method comprises the step:

-   -   issuing an overflow indication in case no unused erase counter        filed was found.

In an embodiment, the overflow indication is used to extend the erasecounter.

Also, a device is provided, the device comprising:

-   -   an erase counter comprising several erase counter fields;    -   a processing unit that is arranged for processing the erase        counter by        -   determining an unused erase counter field;        -   writing a selection code and an address information in the            unused erase counter field;        -   wherein the selection code and the address information are            combined to determine at least one physical address of a            memory.

Said processing unit may be any processing device that may be providedtogether with the memory on the same chip or die or external to thememory. The processing unit may comprise portions of hardware, softwareand/or firmware. The processing unit may be arranged in a distributedway among several components or it may be a single piece of hardware.

It is noted that the features described with regard to the method may beapplicable for the device(s) mentioned herein as well. This applies inparticular for the processing unit, which may conduct the stepsdescribed in view of the method.

In an embodiment, the device further comprises a memory portion, whereinthe processing unit is arranged for processing the erase counter basedon an erase procedure to be conducted on the memory portion.

The memory portion may be a sector or a page of a (non-volatile) memory.The memory portion may be erased in a single erase step. The erasecounter may be a physical part of the memory that also contains thememory portion. As an alternative, the erase counter may be located on aseparate memory device. The erase counter may be a counter codedaccording to an unary code, e.g., a thermometer code.

In an embodiment, the processing unit is arranged for

-   -   reading the erase counter and storing it in a register;    -   searching for the unused erase counter field;    -   writing the selection code and the address information in the        unused erase counter field; and    -   writing the register back to the erase counter.

In an embodiment, the device is implemented on a single chip or die.

The device may in particular be a (single) chip or an arrangementcomprising several chips. A chip may comprise an integrated circuit, adie and/or a semiconductor device.

In an embodiment, the memory portion is part of a non-volatile memory.

In an embodiment, the memory portion comprises at least one of thefollowing

-   -   floating gate cells;    -   PCRAM,    -   RRAM,    -   MRAM,    -   MONOS devices,    -   nano crystal cells,    -   FeRAM,    -   hard drive,    -   non-volatile storage.

In an embodiment, the erase counter is arranged such that it is notaccessible to an application software or that it is read-only to theapplication software.

A device is suggested for processing an erase counter comprising erasecounter fields, the device comprising:

-   -   means for determining an unused erase counter field;    -   means for writing a selection code and an address information in        the unused erase counter field;    -   means for wherein the selection code and the address information        are combined to determine at least one physical address of a        memory.

A computer program product is suggested, directly loadable into a memoryof a digital processing device, comprising software code portions forperforming the steps of the method as described herein.

In one or more examples, the functions described herein may beimplemented at least partially in hardware, such as specific hardwarecomponents or a processor. More generally, the techniques may beimplemented in hardware, processors, software, firmware, or anycombination thereof. If implemented in software, the functions may bestored on or transmitted over as one or more instructions or code on acomputer-readable medium and executed by a hardware-based processingunit. Computer-readable media may include computer-readable storagemedia, which corresponds to a tangible medium such as data storagemedia, or communication media including any medium that facilitatestransfer of a computer program from one place to another, e.g.,according to a communication protocol. In this manner, computer-readablemedia generally may correspond to (1) tangible computer-readable storagemedia which is non-transitory or (2) a communication medium such as asignal or carrier wave. Data storage media may be any available mediathat can be accessed by one or more computers or one or more processorsto retrieve instructions, code and/or data structures for implementationof the techniques described in this disclosure. A computer programproduct may include a computer-readable medium.

By way of example, and not limitation, such computer-readable storagemedia can comprise RAM, ROM, EEPROM, CD-ROM or other optical diskstorage, magnetic disk storage, or other magnetic storage devices, flashmemory, or any other medium that can be used to store desired programcode in the form of instructions or data structures and that can beaccessed by a computer. Also, any connection is properly termed acomputer-readable medium, i.e., a computer-readable transmission medium.For example, if instructions are transmitted from a website, server, orother remote source using a coaxial cable, fiber optic cable, twistedpair, digital subscriber line (DSL), or wireless technologies such asinfrared, radio, and microwave, then the coaxial cable, fiber opticcable, twisted pair, DSL, or wireless technologies such as infrared,radio, and microwave are included in the definition of medium. It shouldbe understood, however, that computer-readable storage media and datastorage media do not include connections, carrier waves, signals, orother transient media, but are instead directed to non-transient,tangible storage media. Disk and disc, as used herein, includes compactdisc (CD), laser disc, optical disc, digital versatile disc (DVD),floppy disk and Blu-ray disc where disks usually reproduce datamagnetically, while discs reproduce data optically with lasers.Combinations of the above should also be included within the scope ofcomputer-readable media.

Instructions may be executed by one or more processors, such as one ormore central processing units (CPU), digital signal processors (DSPs),general purpose microprocessors, application specific integratedcircuits (ASICs), field programmable logic arrays (FPGAs), or otherequivalent integrated or discrete logic circuitry. Accordingly, the term“processor”, as used herein may refer to any of the foregoing structureor any other structure suitable for implementation of the techniquesdescribed herein. In addition, in some aspects, the functionalitydescribed herein may be provided within dedicated hardware and/orsoftware modules configured for encoding and decoding, or incorporatedin a combined codec. Also, the techniques could be fully implemented inone or more circuits or logic elements.

The techniques of this disclosure may be implemented in a wide varietyof devices or apparatuses, including a wireless handset, an integratedcircuit (IC) or a set of ICs (e.g., a chip set). Various components,modules, or units are described in this disclosure to emphasizefunctional aspects of devices configured to perform the disclosedtechniques, but do not necessarily require realization by differenthardware units. Rather, as described above, various units may becombined in a single hardware unit or provided by a collection ofinteroperative hardware units, including one or more processors asdescribed above, in conjunction with suitable software and/or firmware.

Although various exemplary embodiments of the invention have beendisclosed, it will be apparent to those skilled in the art that variouschanges and modifications can be made which will achieve some of theadvantages of the invention without departing from the spirit and scopeof the invention. It will be obvious to those reasonably skilled in theart that other components performing the same functions may be suitablysubstituted. It should be mentioned that features explained withreference to a specific figure may be combined with features of otherfigures, even in those cases in which this has not explicitly beenmentioned. Further, the methods of the invention may be achieved ineither all software implementations, using the appropriate processorinstructions, or in hybrid implementations that utilize a combination ofhardware logic and software logic to achieve the same results. Suchmodifications to the inventive concept are intended to be covered by theappended claims.

1. A method for processing an erase counter comprising erase counterfields, the method comprising the steps: determining an unused erasecounter field; writing a selection code and an address information inthe unused erase counter field; wherein the selection code and theaddress information are combined to determine at least one physicaladdress of a memory.
 2. The method according to claim 1, wherein thephysical address of the memory is directed to a sector or to a page ofthe memory.
 3. The method according to claim 2, wherein at least onesector or at least one page of the memory is subject to an eraseoperation.
 4. The method according to claim 3, wherein the eraseoperation is triggered or conducted prior to said processing of theerase counter or after said processing of the erase counter.
 5. Themethod according to claim 1, wherein the selection code and the addressinformation are combined to determine several physical addresses of thememory.
 6. The method according to claim 1, wherein the selection codedetermines one or several physical addresses within the addressinformation.
 7. The method according to claim 1, further comprising thesteps: aligning the selection code at the least significant bit with theaddress information determining at least one physical address that issubject to an erase operation by combining the selecting code and theaddress information, wherein a first of the selection code indicatesthat a corresponding bit of the address information remains unchanged ora second value of the selection code indicates that a corresponding bitof the address information may be either “0” or “1”.
 8. The methodaccording to claim 7, wherein the first value is “0” and the secondvalue is “1”.
 9. The method according to claim 1, wherein determining anunused erase counter field comprises conducting a search operation forthe unused erased counter field in an erase counter storage provided forthe erase counter.
 10. The method according to claim 1, wherein theerase counter is incremented by writing the selection code and theaddress information to the unused erase counter field.
 11. The methodaccording to claim 1, wherein the erase counter is associated with aportion of a memory, in particular a non-volatile memory, and wherein anerase operation applied to said portion of the memory triggersincrementing the erase counter.
 12. The method according to claim 1,wherein the erase counter is part of a non-volatile memory, wherein thememory of the erase counter is not accessible or read-only to anapplication software.
 13. The method according to claim 1, wherein eachlogical bit of the erase counter field comprises several physical bits,wherein a majority decision is made based on the several physical bitsfor the corresponding logical bit.
 14. The method according to claim 1,the method further comprising the steps: reading the erase counter andstoring it in a register; searching for the unused erase counter field;writing the selection code and the address information in the unusederase counter field; and writing the register back to the erase counter.15. The method according to claim 14, comprising the step: indicating awarning or an error in case writing the register back to the erasecounter was not successful.
 16. A device comprising an erase countercomprising several erase counter fields; a processing unit that isarranged for processing the erase counter by determining an unused erasecounter field; writing a selection code and an address information inthe unused erase counter field; wherein the selection code and theaddress information are combined to determine at least one physicaladdress of a memory.
 17. The device according to claim 16, furthercomprising a memory portion, wherein the processing unit is arranged forprocessing the erase counter based on an erase procedure to be conductedon the memory portion.
 18. The device according to claim 16, wherein theprocessing unit is arranged for reading the erase counter and storing itin a register; searching for the unused erase counter field; writing theselection code and the address information in the unused erase counterfield; and writing the register back to the erase counter.
 19. Thedevice according to claim 16, wherein the device is implemented on asingle chip or die.
 20. The device according to claim 16, wherein thememory portion is part of a non-volatile memory.
 21. The deviceaccording to claim 16, wherein the memory portion comprises at least oneof the following floating gate cells; PCRAM, RRAM, MRAM, MONOS devices,nano crystal cells, FeRAM, hard drive, non-volatile storage.
 22. Adevice for processing an erase counter comprising erase counter fields,the device comprising: means for determining an unused erase counterfield; means for writing a selection code and an address information inthe unused erase counter field; means for wherein the selection code andthe address information are combined to determine at least one physicaladdress of a memory.
 23. A computer program product directly loadableinto a memory of a digital processing device, comprising software codeportions for performing the steps of the method according to claim 1.